赛普拉斯半导体Corp. (NASDAQ: CY), the Static Random Access Memory (SRAM) market leader, announced the availability of the industry’s highest-density synchronous SRAMs with on-chip Error-Correcting Code (ECC). The integrated ECC feature enables the new 36Mb synchronous SRAMs to provide the highest levels of data reliability, simplifying designs for a wide variety of military, communication and data processing applications. Cypress plans to expand the family of high-performance synchronous SRAMs with ECC with additional densities this year.
Soft errors caused by background radiation can corrupt memory content, resulting in a loss of critical data. A hardware ECC block in Cypress’s new synchronous SRAMs performs all error correction functions inline, without user intervention, delivering best-in-class Soft Error Rate (SER) performance. The synchronous SRAMs with ECC are pin-compatible with current synchronous SRAMs, enabling customers to enhance SER and system reliability while retaining board layout. Additionally, the new SRAMs help reduce power consumption by as much as 36% over competing solutions. A video introducing Cypress’s synchronous SRAMs with ECC is available at www.cypress.com/syncECCvideo.
“赛普拉斯是同步SRAM的全球市场领导者，这款带有片上ECC的新款设备系列展示了我们对扩展我们的标准同步，Nobl®和QDR®SRAM的组合，”Oliver Pohland（Oliver Pohland）同步赛普拉姆斯的SRAM。“与我们的整个SRAM投资组合一样，这些新设备由赛普拉斯最可达的制造和客户支持支持。”
可用性
The new 36Mb synchronous SRAMs are currently available in industrial temperature grade in RoHS-compliant 100-pin TQFP and 165-ball BGA packages.
赛普拉斯半导体
www.cypress.com
帖子同步SRAM系列体育运动片上纠错鳕鱼首先出现了微控制器提示.
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